View SFC05-4_4533848.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PROTECTION PRODUCTS Description
The SFC05-4 is a quad flip chip TVS array. They are state-of-the-art devices that utilize solid-state siliconavalanche technology for superior clamping performance and DC electrical characteristics. The SFC series TVS diodes are designed to protect sensitive semiconductor components from damage or latch-up due to electrostatic discharge (ESD) and other voltage induced transient events. The SFC05-4 is a 6-bump, 0.5mm pitch flip chip array with a 3x2 bump grid. It measures 1.5 x 1.0 x 0.65mm. This small outline makes the SFC05-4 especially well suited for portable applications. Flip chip TVS devices are compatible with current pick and place equipment and assembly methods. Each device will protect up to four data or I/O lines. The flip chip design results in lower inductance, virtually eliminating voltage overshoot due to leads and interconnecting bond wires. They may be used to meet the ESD immunity requirements of IEC 61000-4-2, Level 4 (15kV air, 8kV contact discharge).
ChipClamp Flip Chip TVS Diode Array
PRELIMINARY Features
300 Watts peak pulse power (tp = 8/20s) Transient protection for data lines to IEC 61000-4-2 (ESD) 15kV (air), 8kV (contact) IEC 61000-4-4 (EFT) 40A (5/50ns) IEC 61000-4-5 (Lightning) 24A (8/20s) Small chip scale package requires less board space Low profile (< 0.65mm) No need for underfill material Protects four I/O or data lines Low clamping voltage Working voltage: 5V Solid-state silicon-avalanche technology
SFC05-4
Mechanical Characteristics
JEDEC MO-211, 0.50 mm Pitch Flip Chip Package Non-conductive top side coating Marking : Marking Code Packaging : Tape and Reel
Applications
Cell Phone Handsets and Accessories Personal Digital Assistants (PDA's) Notebook and Hand Held Computers Portable Instrumentation Smart Cards MP3 Players GPS
Device Dimensions
Schematic & PIN Configuration
SFC05-4 Maximum Dimensions (mm)
3 x 2 Grid CSP TVS (Bottom View)
Revision 8/11/04
1
www.semtech.com
SFC05-4
PROTECTION PRODUCTS Absolute Maximum Rating
R ating Peak Pulse Power (tp = 8/20s) Peak Pulse Current (tp = 8/20s) ESD p er IEC 61000-4-2 (Air) ESD p er IEC 61000-4-2 (Contact) Op erating Temp erature Storage Temp erature Symbol Pp k IP P VESD TJ TSTG Value 300 24 >25 >15 -55 to +125 -55 to +150
PRELIMINARY
Units Watts A kV C C
Electrical Characteristics
Parameter Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current Clamping Voltage Clamping Voltage Junction Capacitance Symbol VRWM V BR IR VC VC Cj It = 1mA VRWM = 5V, T=25C IPP = 5A, tp = 8/20s Any I/O to Ground IPP = 24A, tp = 8/20s Any I/O to Ground VR = 0V, f = 1MHz 6 10 9.5 11 350 Conditions Minimum Typical Maximum 5 Units V V A V V pF
2004 Semtech Corp.
2
www.semtech.com
SFC05-4
PROTECTION PRODUCTS Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
10
110
PRELIMINARY
Power Derating Curve
Peak Pulse Power - Ppk (kW)
100 % of Rated Power or PP I 90 80 70 60 50 40 30 20 10 0
1
0.1
0.01 0.1 1 10 Pulse Duration - tp (s) 100 1000
0
25
50
75
100
125
150
Ambient Temperature - TA (oC)
Pulse Waveform
110 100 90 80 Percent of IPP 70 60 50 40 30 20 10 0 0 5 10 15 Time (s) 20 25 30 td = IPP/2 e
-t
Clamping Voltage vs. Peak Pulse Current
10.00
Waveform Parameters: tr = 8s td = 20s
9.00 Clamping Voltage - VC (V) 8.00 7.00 6.00 5.00 4.00 3.00 2.00 1.00 0.00 0 5 10 15 20 25 30 Peak Pulse Current - I PP (A) Waveform Parameters: tr = 8s td = 20s
Forward Voltage vs. Forward Current
4
300
Capacitance vs. Reverse Voltage
250
Forward Voltage -V F (V)
3
Capacitance - Cj (pF)
200
2
150
1
100
Waveform Parameters: tr = 8s td = 20s
0 10 20 30 40 50
50
0
0 0 1 2 3 4
f = 1MHz
5
Forward Current - IF (A)
Reverse Voltage - VR (V)
2004 Semtech Corp.
3
www.semtech.com
SFC05-4
PROTECTION PRODUCTS Typical Characteristics (Continued)
ESD Clamping (8kV Contact Discharge)
PRELIMINARY
2004 Semtech Corp.
4
www.semtech.com
SFC05-4
PROTECTION PRODUCTS Applications Information
Device Connection Options The SFC05-4 has solder bumps located in a 3 x 2 matrix layout on the active side of the device. The bumps are designated by the numbers 1 - 3 along the horizontal axis and letters A - B along the vertical axis. The lines to be protected are connected at bumps A1, B1, A3, and B3. Bumps A2 and B2 are connected to ground. All path lengths should be kept as short as possible to minimize the effects of parasitic inductance in the board traces. Flip Chip TVS Flip chip TVS devices are wafer level chip scale packages. They eliminate external plastic packages and leads and thus result in a significant board space savings. Manufacturing costs are minimized since they do not require an intermediate level interconnect or interposer layer for reliable operation. Their compatibility with current pick and place equipment further reduces manufacturing costs. Certain precautions and design considerations have to be observed, however, for maximum solder joint reliability. These include solder pad definition, board finish, and assembly parameters. Printed Circuit Board Mounting Non-solder mask defined (NSMD) land patterns are recommended for mounting the SFC05-4. Solder mask defined (SMD) pads produce stress points near the solder mask on the PCB side that can result in solder joint cracking when exposed to extreme fatigue conditions. The recommended pad size is 0.225 0.010 mm with a solder mask opening of 0.350 0.025 mm. Grid Courtyard The recommended grid placement courtyard is 1.3 x 1.8 mm. The grid courtyard is intended to encompass the land pattern and the component body that is centered in the land pattern. When placing parts on a PCB, the highest recommended density is when one courtyard touches another.
To Connector
PRELIMINARY
Device Schematic and Pin Configuration
Layout Example
To Protected IC Ground To Protected IC
NSMD Package Footprint
2004 Semtech Corp.
5
www.semtech.com
SFC05-4
PROTECTION PRODUCTS Applications Information (Continued)
Printed Circuit Board Finish A uniform board finish is critical for good assembly yield. Two finishes that provide uniform surface coatings are immersion nickel gold and organic surface protectant (OSP). A non-uniform finish such as hot air solder leveling (HASL) can lead to mounting problems and should be avoided. Stencil Design A properly designed stencil is key to achieving adequate solder volume without compromising assembly yields. A 0.100mm thick, laser cut, electro-polished stencil with 0.275mm square apertures and rounded corners is recommended. Reflow Profile The flip chip TVS can be assembled using the reflow requirements for IPC/JEDEC standard J-STD-020 for assembly of small body components. During reflow, the component will self-align itself on the pad. Circuit Board Layout Recommendations for Suppression of ESD Good circuit board layout is critical for the suppression of ESD induced transients. The following guidelines are recommended: Place the TVS near the input terminals or connectors to restrict transient coupling. Minimize the path length between the TVS and the protected line. Minimize all conductive loops including power and ground loops. The ESD transient return path to ground should be kept as short as possible. Never run critical signals near board edges. Use ground planes whenever possible. Stencil Design
PRELIMINARY
Assembly Guideline for Pb-Free Soldering The following are recommendations for the assembly of this device:
Assembly Parameter Solder Ball Comp osition Solder Stencil Design Solder Stencil Thickness Solder Paste Comp osition Solder Paste Typ e Solder Reflow Profile PCB Solder Pad Design PCB Pad Finish R ecommendation 95.5Sn/3.8Ag/0.7Cu Same as the SnPb design 0.100 mm (0.004") Sn Ag (3-4) Cu (0.5-0.9) Typ e 4 size sp here or smaller p er JEDEC J-STD-020 Same as the SnPb Design OSP or AuN i
2004 Semtech Corp.
6
www.semtech.com
SFC05-4
PROTECTION PRODUCTS Outline Drawing - 3x2 Grid Flip Chip
A 1.470.03 B
PRELIMINARY
INDEX AREA A1 CORNER
0.970.03
0.10 C 0.40-0.60 0.50-0.75
C 0.05 C 0.50 B 0.50 A 1 2
3.
0.1500.025 6X O0.175-0.225 0.005 CAB
3
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS 2. REFERENCE JEDEC REGISTRATION MO-211. 3. Sn63/Pb37 FOR STANDARD DEVICES OR SN95.5/Ag3.8/Cu0.7 FOR Pb-FREE DEVICES
Land Pattern - 3x2 Grid Flip Chip
2004 Semtech Corp.
7
www.semtech.com
SFC05-4
PROTECTION PRODUCTS Marking Codes
Part Number SFC05-4 Marking Code F45U
PRELIMINARY Ordering Information
Part Number SFC05-4.WC SFC05-4.WCT
(1)
Pitch Option 2mm 2mm
Qty per Reel 3,000 3,000
R eel Size 7 Inch 7 Inch
Top Coating: The top (non-bump side) of the device is a white non-conductive coating. The coating is laser markable and increases mechanical durability. This material is compliant with UL 94V-0 flammability requirements.
Notes (1) Lead Free Solder Balls
ChipClamp is a mark of Semtech Corporation
Tape and Reel Specification
Pin A1 Pin A1 Pin A1
Tape Specifications
Device Orientation
Contact Information
Semtech Corporation Protection Products Division 200 Flynn Rd., Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
2004 Semtech Corp. 8 www.semtech.com

▲Up To Search▲

Price & Availability of SFC05-4

	To Download SFC05-4 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .